A synchronous memory device and a method of controlling the memory device. The memory device including at least one memory section having a plurality of memory cells. The memory device includes a first internal register to store a value which is indicative of a number of clock cycles to transpire before...http://www.google.de/patents/US6415339?utm_source=gb-gplus-sharePatent US6415339 - Memory device having a plurality of programmable internal registers and a delay time register
