An instruction fetch unit in which an early instruction fetch is initiated to access a main memory simultaneously with checking a cache for the desired instruction. On a slow path to main memory is a large main translation lookaside buffer (TLB) that holds address translations. On a fast path is a smaller...http://www.google.de/patents/US5423014?utm_source=gb-gplus-sharePatent US5423014 - Instruction fetch unit with early instruction fetch mechanism
