In one embodiment, a processor comprises a cache and a cache miss unit coupled to the cache. The cache is coupled to be accessed by cache accesses corresponding to a plurality of threads active in the processor. The cache miss unit is configured to record a plurality of cache misses detected in the cache...http://www.google.de/patents/US8037250?utm_source=gb-gplus-sharePatent US8037250 - Arbitrating cache misses in a multithreaded/multi-core processor
