In an FPGA having four-input lookup tables (LUTs) with parallel two-input AND gates receiving two of the four LUT input signals, associated registers, and a carry chain receiving one input signal from the AND gate output, a loadable up-down counter is formed by connecting the register output to one of...http://www.google.de/patents/US6157209?utm_source=gb-gplus-sharePatent US6157209 - Loadable up-down counter with asynchronous reset
