A power-on reset circuit has a power-on level detecting circuit which detects a power voltage to output a power-on reset signal and a delay circuit which delays the power-on reset signal output by the power-on level detecting circuit. Two chip address specifying pads are connected to the delay circuit....http://www.google.de/patents/US7196950?utm_source=gb-gplus-sharePatent US7196950 - Non-volatile semiconductor storage device performing ROM read operation upon power-on
