A process of forming a transistor with three vertical gate electrodes including a high-k gate dielectric and the resulting transistor. By forming such a transistor it is possible to maintain an acceptable aspect ratio as MOSFET structures are scaled down to sub-micron sizes. The transistor gate electrodes...http://www.google.de/patents/US20050145959?utm_source=gb-gplus-sharePatent US20050145959 - Technique to mitigate short channel effects with vertical gate transistor with different gate materials
