An input buffer circuit is disclosed. The circuit has a single stage circuit portion for receiving a multiplexed row address bit and a multiplexed column address bit. Circuitry is connected to the single stage circuit portion for separately holding the received multiplexed row address bit and the received...http://www.google.de/patents/US5191555?utm_source=gb-gplus-sharePatent US5191555 - CMOS single input buffer for multiplexed inputs
