To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock...http://www.google.de/patents/US7307900?utm_source=gb-gplus-sharePatent US7307900 - Method and apparatus for optimizing strobe to clock relationship
