The present invention provides a method and system for comparing a pair of circuit models without the need for performing a false negative check when cut-points are introduced. An exemplary method includes generating a BDD for each of a plurality of signals of each circuit model from an initial cut-point...http://www.google.de/patents/US20020108093?utm_source=gb-gplus-sharePatent US20020108093 - Method and system for formal verification of a circuit model
