In a preferred embodiment, the invention uses an 8-to-1 data serialization circuit in the transmitter to convert 80-bit parallel 200 MHz data to 10-bit parallel 1.6 Mb/s date. On the receiver side, data are captured using a forwarded clock and de-serialized. A single global DLL generates 16 master phases...http://www.google.de/patents/US6418537?utm_source=gb-gplus-sharePatent US6418537 - Accurate timing calibration for each of multiple high-speed clocked receivers using a single DLL
