An instruction dispatch apparatus is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program order is retained until the succeeding clock cycle. During the succeeding clock cycle, a microcode unit...http://www.google.de/patents/US5867680?utm_source=gb-gplus-sharePatent US5867680 - Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions
