In the dynamic process for the generation of biased pseudo-random test patterns for the functional verification of integrated circuit designs, the verification is performed in a sequence of steps, with each test pattern providing all data required to test a circuit design during at least one of said...http://www.google.de/patents/US5202889?utm_source=gb-gplus-sharePatent US5202889 - Dynamic process for the generation of biased pseudo-random test patterns for the functional verification of hardware designs
