A programmable logic device is provided with phase-locked loop ("PLL") or delay-locked loop ("DLL" ) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In...http://www.google.de/patents/US20010000426?utm_source=gb-gplus-sharePatent US20010000426 - Phase-locked loop or delay-locked loop circuitry for programmable logic devices
