A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 microns. The deep n-well is a grid structure...http://www.google.de/patents/US7747974?utm_source=gb-gplus-sharePatent US7747974 - Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure
