The present invention is a method and apparatus to verify a design which has an input space and a predicate. The input space is decomposed into a plurality of decompositions. The input space includes a plurality of node variables. The plurality of decompositions includes parametric variables. The decompositions...http://www.google.de/patents/US6539345?utm_source=gb-gplus-sharePatent US6539345 - Symbolic simulation using input space decomposition via Boolean functional representation in parametric form
