In one embodiment, an interconnect object in a layout of an integrated circuit design to be created with a photolithographic process is determined. The interconnect object includes a width and a length in the layout. A contour generation of the interconnect object in a drawn design is determined based...http://www.google.de/patents/US8015510?utm_source=gb-gplus-sharePatent US8015510 - Interconnection modeling for semiconductor fabrication process effects
