A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock...http://www.google.de/patents/US6507532?utm_source=gb-gplus-sharePatent US6507532 - Semiconductor memory device having row-related circuit operating at high speed
