An instruction cache memory (12) includes a clock gate circuit (26) for controlling the supply of a clock signal (CLK) to tag RAM (22). The clock gate circuit (22) supplies the clock signal (CLK) to tag RAM 22 only when there is a movement in cache line for storing a word to be read out or a branch instruction...http://www.google.de/patents/US6345336?utm_source=gb-gplus-sharePatent US6345336 - Instruction cache memory includes a clock gate circuit for selectively supplying a clock signal to tag RAM to reduce power consumption
