A memory control circuit for controlling a memory bus and a memory includes buffers, counters, data transfer circuits, and a bus arbiter having a state machine. Each of the data transfer circuits transmits a request signal demanding start of the data transfer on the basis of at least one of the count...http://www.google.de/patents/US6754786?utm_source=gb-gplus-sharePatent US6754786 - Memory control circuit and method for arbitrating memory bus
