A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies...http://www.google.de/patents/US5911153?utm_source=gb-gplus-sharePatent US5911153 - Memory design which facilitates incremental fetch and store requests off applied base address requests
