A interleaved channeless gate array architecture for fabricating very large scale integration circuits created in a gate array comprises a plurality of rows or columns of basic cells wherein each of the cells includes a pair arrangement of complementary channel MOS transistors formed in adjacently disposed...http://www.google.de/patents/US5079614?utm_source=gb-gplus-sharePatent US5079614 - Gate array architecture with basic cell interleaved gate electrodes
