A cache coherency protocol for a multi-processor system which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory. The transitional data state occurs when a processor requests from main memory a data block...http://www.google.de/patents/US5297269?utm_source=gb-gplus-sharePatent US5297269 - Cache coherency protocol for multi processor computer system
