A method of fabricating a CMOS device having (1) an anti-SCE block region below a channel region and (2) a metal gate. The invention uses a masking layer having an opening to define the anti-SCE block implant and also the gate structure. The method comprises forming a masking layer having a first opening...http://www.google.de/patents/US6232164?utm_source=gb-gplus-sharePatent US6232164 - Process of making CMOS device structure having an anti-SCE block implant
