A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layout...http://www.google.de/patents/US8134185?utm_source=gb-gplus-sharePatent US8134185 - Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned ends
