A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0])...http://www.google.de/patents/US7685402?utm_source=gb-gplus-sharePatent US7685402 - RISC microprocessor architecture implementing multiple typed register sets
