A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued during one clock. If no resource conflicts occur,...http://www.google.de/patents/US5390355?utm_source=gb-gplus-sharePatent US5390355 - Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions
