Disclosed is a biasing circuit for bringing a power FET to a substantial full enhancement. The biasing circuit includes: (a) a rail power voltage that is coupled to a drain terminal of the power field effect transistor; (b) a load being coupled between an other potential and a source terminal of the...http://www.google.de/patents/US6069516?utm_source=gb-gplus-sharePatent US6069516 - Compact voltage biasing circuitry for enhancement of power MOSFET
