In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one...http://www.google.de/patents/US6204541?utm_source=gb-gplus-sharePatent US6204541 - Semiconductor memory
