A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) for the wiring structure, a tolerance (ξC) for...http://www.google.de/patents/US7823114?utm_source=gb-gplus-sharePatent US7823114 - Method of designing wiring structure of semiconductor device and wiring structure designed accordingly
