A matrix comprised of pass transistor cells (81 through 96) forms an address decoder circuit (80). By using pass transistor cells in a matrix format, a decoder which consumes a minimum of power and which may be constructed using a minimum of allotted space in an integrated circuit is achieved....http://www.google.de/patents/US4633220?utm_source=gb-gplus-sharePatent US4633220 - Decoder using pass-transistor networks
