A microprocessor with a dispatch unit which dispatches a maximum number of instructions each cycle, without splitting into separate blocks after a branch instruction. A mispredicted branch is handled by setting a valid bit to invalid for instructions following the branch instruction in an outstanding...http://www.google.de/patents/US5809324?utm_source=gb-gplus-sharePatent US5809324 - Multiple instruction dispatch system for pipelined microprocessor without branch breaks 
