The decode circuit utilizes NPN and PNP transistors and performs a complete decode function in only one logic level with the no need for a true/complement input of each binary input. A first embodiment of the decoder provides an UP level output when selected. A second embodiment of the decoder provides...http://www.google.de/patents/US4494017?utm_source=gb-gplus-sharePatent US4494017 - Complementary decode circuit
