A method and computer program product for modeling a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to the gate structure and disposed above the active device area, the conductive line feature including a conductive...http://www.google.de/patents/US7979815?utm_source=gb-gplus-sharePatent US7979815 - Compact model methodology for PC landing pad lithographic rounding impact on device performance
