A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point...http://www.google.de/patents/US20050044303?utm_source=gb-gplus-sharePatent US20050044303 - Memory system including an integrated circuit buffer device
