Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor...http://www.google.de/patents/US5770881?utm_source=gb-gplus-sharePatent US5770881 - SOI FET design to reduce transient bipolar current
