A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second...http://www.google.de/patents/US5250831?utm_source=gb-gplus-sharePatent US5250831 - DRAM device having a memory cell array of a divided bit line type
