A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to instruction fields, which indicate the address of...http://www.google.de/patents/US5136697?utm_source=gb-gplus-sharePatent US5136697 - System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
