An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system...http://www.google.de/patents/US6249520?utm_source=gb-gplus-sharePatent US6249520 - High-performance non-blocking switch with multiple channel ordering constraints
