An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector...http://www.google.de/patents/US4888689?utm_source=gb-gplus-sharePatent US4888689 - Apparatus and method for improving cache access throughput in pipelined processors
