A method and a chipset for supporting a system management mode interrupt of a multi-processor system. While the central processing is accessing the specified input/output port defined by the chipset, the chipset detects the specified input/output port at the peripheral component interface bus and extracts...http://www.google.de/patents/US6711642?utm_source=gb-gplus-sharePatent US6711642 - Method and chipset for system management mode interrupt of multi-processor supporting system
