A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for...http://www.google.de/patents/US6295600?utm_source=gb-gplus-sharePatent US6295600 - Thread switch on blocked load or store using instruction thread field
