A dedicated block random access memory (RAM) is provided for a programmable logic device (PLD), such as a field programmable gate array (FPGA). The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of parity or non-parity modes for accessing the...http://www.google.de/patents/US6346825?utm_source=gb-gplus-sharePatent US6346825 - Block RAM with configurable data width and parity for use in a field programmable gate array
