A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register...http://www.google.de/patents/US20070115292?utm_source=gb-gplus-sharePatent US20070115292 - GPU Internal Wait/Fence Synchronization Method and Apparatus
