A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer...http://www.google.de/patents/US5097310?utm_source=gb-gplus-sharePatent US5097310 - Complementary semiconductor device having improved device isolating region
