Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a verification sense amplifier, a switch, and an output buffer. The switch alternates electrical connection...http://www.google.de/patents/US6870770?utm_source=gb-gplus-sharePatent US6870770 - Method and architecture to calibrate read operations in synchronous flash memory
