System for testing memory associated with a set of check bits in an EDC system. The circuitry of the invention includes an EDC circuit; multiplexers; and a memory with first storage bits, second storage bits, and third storage bits. In writing data to the memory, a multi-bit data word having a first...http://www.google.de/patents/US5357529?utm_source=gb-gplus-sharePatent US5357529 - Error detecting and correcting apparatus and method with transparent test mode
