A logic which enables implementation of a 80-bit wide or a 96-bit wide cache SRAM using the same memory array. The logic implementation is accomplished by merging tag, and data into an order block of information to maximize bus utilization. The logic reduces the bus cycles from four cycles for an 80-bit...http://www.google.de/patents/US6223253?utm_source=gb-gplus-sharePatent US6223253 - Word selection logic to implement an 80 or 96-bit cache SRAM
