An LDD MIS FET comprises a silicide over the lightly doped regions to reduce the parasitic resistance and to prevent the depletion of the lightly-doped regions, reducing the hot carrier injection effect. By the provision of the silicide, the overall parasitic resistance can be made low. Moreover, the...http://www.google.de/patents/US5028554?utm_source=gb-gplus-sharePatent US5028554 - Process of fabricating an MIS FET
