A parallel test system and method for testing integrated circuit devices which can reliably prevent devices that should not be active due to a blown fuse from generating random data signals which can adversely impact the test results of other chips being tested are disclosed. The state of each fuse that...http://www.google.de/patents/US6275058?utm_source=gb-gplus-sharePatent US6275058 - Method and apparatus for properly disabling high current parts in a parallel test environment
