A method of computing parasitic capacitances between multiple electrical conductors within an electric circuit computes a division of the circuit's physical layout into a plurality of windows. The parasitic capacitances associated with the conductors of each window are computed, and the results for the...http://www.google.de/patents/US5452224?utm_source=gb-gplus-sharePatent US5452224 - Method of computing multi-conductor parasitic capacitances for VLSI circuits
